• November 2024 - I enjoyed speaking today at the "Cyber Security and Trustworthy Systems Researchers Meet" at UNSW CSE on the Large Language Models + Cybersecurity work I and the team have done over the last three years.

• November 2024 - I was part of a panel "Engineering the Future: Unlocking the Digital Frontier" hosted by UNSW CSE:

  • https://www.youtube.com/watch?v=VVWAmzQt7LM 

• October 2024 - I remotely presented mine and Benjamin Tan's accepted vision paper at TPS 2024 "Large Language Models for Hardware Security (invited, short paper)".

• October 2024 - It's the kickoff for AI-HDL, a global AI for hardware competition that I am helping to organise with Prof. Soheil at University of Arizona!

  • https://csm.arizona.edu/AIHDL 

• October 2024 - I took part in the UNSW CSE Undergraduate Open Labs day, showing off some of the new hardware we've been developing for the new hardware security course and the FPGA project courses.

• October 2024 - I delivered an invited talk "Chip-Chat: The Path Towards Generating Hardware with Generative AI" for a group of Meta engineers.

• August 2024 - I and my students Jiamin Chang and Siyu Qiu delivered posters on our research works at the "21st Annual International Conference on Privacy, Security, and Trust (PST2024)" held at UNSW Sydney.

• August 2024 - Intel has renewed the research grant for myself and my colleague Benjamin Tan at University of Calgary which provides funding towards our project "IF-THEN-AI: Improving (Security & Design) Feedback of Tools for Hardware Engineering with Generative AI". 

• July 2024 - I'm at the Brain-Link X Lab symposium on Security, Privacy, and Trust in AI, held in South Korea. I'll be presenting on multiple days at this venue, check it out at https://ai-security.org 

• July 2024 - I presented with my student Siyu (Annie) at an internal seminar at SRI International in Melo Park, California on the various projects our group does at the intersection of LLMs and hardware design.

• June/July 2024 - Myself and my student Siyu (Annie) attended LAD'24 to present our work on "LLM-aided explanations of EDA synthesis errors" at the beautiful IBM Almaden campus. 

• May 2024 - I presented an Intel IPAS seminar on how our research group is approaching the opportunities Generative AI give us for applications in hardware, with my vision for accelerating design, democratizing development, and improving the state of the art in hardware security.

• April 2024 - My new Hardware Security course, COMP6420, is announced and will be available to enroll in at UNSW from 2025!

• March 2024 - I am at the ACM SIGCSE conference delivering work with my colleagues Sasha Vassar and Jake Renzella on our work using Generative AI for error messages in C!

  • https://dl.acm.org/doi/abs/10.1145/3626252.3630822 

• March 2024 - Enjoyed delivering a seminar today on my vision towards using Generative AI for designing hardware at the Synopsys innovation speaker series!

• February 2024 - I am at the ISSCC Panel "Generative AI for Chip Design" - feel free to drop by!

• February 2024 - Delighted to deliver a seminar on the Generative AI for Hardware today at Google!

• February 2024 - Our Generative AI for Hardware work was featured in a broader piece by the Wall Street Journal!

  • https://www.wsj.com/articles/designing-chips-is-getting-harder-these-engineers-say-chatbots-and-ai-can-help-092b4c49

• August 2023 - I and my colleague Benjamin Tan at University of Calgary have been awarded from Intel a research gift which provides funding towards our project "IF-THEN-AI: Improving (Security & Design) Feedback of Tools for Hardware Engineering with Generative AI".

• July 2023 - I started at UNSW  School of Computer Science and Engineering today as a tenure-track Lecturer (equivalent to USA "Assistant Professor")! Hello to my new colleagues, I'm really excited to be here in Sydney, Australia!

• June 2023 - Our Chip-Chat work was featured on Tom's Hardware!

  • https://www.tomshardware.com/news/conversation-with-chatgpt-was-enough-to-develop-part-of-a-cpu 

• June 2023 - Delighted to report that after building on the Tiny Tapeout research, my design (the QTCore-C1) was the winner of the inagural Efabless AI-Generated Silicon Design Challenge:

  • https://efabless.com/ai-generated-design-contest | https://efabless.com/hammond-first-place-winner 

  • https://www.globenewswire.com/news-release/2023/06/08/2684821/0/en/Efabless-Reveals-Winners-of-AI-Generated-Silicon-Design-Challenge.html 

• June 2023 - I and Jason Blocklove were interviewed by Matt Venn of ZeroToAsic about our (potentially world-first!) work to get AI-generated HDL into a chip tapeout:

  • https://www.youtube.com/watch?v=6vC3t_soJok

• May 2023 - Come and see our presentation at this year's IEEE Symposium on Security and Privacy (SP / Oakland!)

  • Publication teaser video: https://www.youtube.com/watch?v=dEDCpOFo-LY

• Delighted to share that three of the masters students I have supervised at NYU are graduating today, congratulations Judy Chang, Mudit Bhargava, and Zhenxing Fan!

• April 2023 - We just submitted potentially the world's first AI-driven HDL for tapeout in Tiny Tapeout 3!

  • See https://github.com/kiwih/tt03-verilog-qtcoreA1

• January 2023 - I am very excited to announce that I will be joining the University of New South Wales (UNSW) Sydney's School of Computer Science and Engineering as a tenure-track faculty ("Lecturer", equivalent to USA "Assistant Professor").

• November 2022 - I presented a briefing on our Large Language Model research at this year's CSAW at NYU.

• May 2022 - we won a distinguished paper award for our publication 'Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributions' at IEEE Symposium on Security and Privacy (SP / Oakland)!

  • Publication teaser video: https://www.youtube.com/watch?v=SxwVnGRkZ7I 

  • Publication presentation official recording: https://www.youtube.com/watch?v=D0aFrzOkLrU 

• May 2022 - excited to announce that we will be presenting a Black Hat Briefing this year in Las Vegas - keep an eye out for 'In Need of 'Pair' Review: Vulnerable Code Contributions by GitHub Copilot'

  • Briefing official recording: https://www.youtube.com/watch?v=xz-zs7GRQ7U 

• March 2022 - Based on my work on GitHub Copilot cybersecurity, I am quoted in CS Online: Why you can't trust AI-generated autocomplete code to be secure 

• January 2022 - I gave a (virtual) talk at Intel, as part of their IPAS Tech Sharing Forum on my GitHub Copilot cybersecurity work.

• January 2022 - I am promoted to Research Assistant Professor in NYU Tandon.

• May 2021 - I gave a (virtual) talk at ASTM International Conference on Additive Manufacturing (ASTM ICAM) on my 3D printer bootloader cybersecurity work

• March 2021 - Based on my work on GitHub Copilot cybersecurity, I am quoted in Wired: It’s Like GPT-3 but for Code—Fun, Fast, and Full of Flaws 

• September 2020 - Based on my work on writing code with Large Language Models, I am quoted in Hackaday: I’m Sorry Dave, You Shouldn’t Write Verilog 

• June 2020 - I begin work as a post-doctoral research associate at NYU Tandon Department of Electrical and Computer Engineering and NYU Center for Cybersecurity with my supervisor Ramesh Karri. My work will focus on cyber-physical system cybersecurity.

• February 2020 - I successfully defend my Ph.D. thesis. A special thanks to my supervisors Partha Roop and Morteza Biglari-Abhari!

• "Systematic Study of Cybersecurity Threats for Smart Inverters", S Karumba, SCK Chau, H Pearce, M Ahmed, H Janicke, Proceedings of the 15th ACM International Conference on Future and Sustainable Energy Systems. 2024.

• "LLMs Cannot Reliably Identify and Reason About Security Vulnerabilities (Yet?): A Comprehensive Evaluation, Framework, and Benchmarks", S Ullah, M Han, S Pujar, H Pearce, A Coskun, G Stringhini, IEEE Symposium on Security and Privacy (SP / Oakland). 2024.

• "Verigen: A large language model for verilog code generation", S Thakur, B Ahmad, H Pearce, B Tan, B Dolan-Gavitt, R Karri, S Garg, ACM Transactions on Design Automation of Electronic Systems (TODAES). 2024.

• "dcc--help: Transforming the Role of the Compiler by Generating Context-Aware Error Explanations with Large Language Models", A Taylor, A Vassar, J Renzella, H Pearce, ACM SIGCSE. 2024.

• "On hardware security bug code fixes by prompting large language models", B Ahmad, S Thakur, B Tan, R Karri, H Pearce, IEEE Transactions on Information Forensics and Security (TIFS). 2024.

• "(Security) Assertions by Large Language Models", R Kande, H Pearce, B Tan, B Dolan-Gavitt, S Thakur, R Karri, J Rajendran, IEEE Transactions on Information Forensics and Security (TIFS). 2024.

• "Scalable Security Enforcement for Cyber Physical Systems", A Baird, A Panda, H Pearce, S Pinisetty, P Roop , IEEE Access. 2024.

• "Netlist Whisperer: AI and NLP Fight Circuit Leakage!", M Nair, R Sadhukhan, H Pearce, D Mukhopadhyay, R Karri, Proceedings of the 2023 Workshop on Attacks and Solutions in Hardware Security. 2023.

• "An Integrated Testbed for Trojans in Printed Circuit Boards with Fuzzing Capabilities", P. Krishnamurthy, H. Pearce, V.R. Surabhi, J. Trujillo, R. Karri, F. Khorrami. IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS). 2023.

• "Examining Zero-Shot Vulnerability Repair with Large Language Models", H. Pearce, B. Tan, B. Ahmad, R. Karri, B. Dolan-Gavitt. IEEE Symposium on Security and Privacy (SP / Oakland). 2023.

• "High-Level Approaches to Hardware Security: A Tutorial". H. Pearce, R. Karri, B. Tan. ACM Transactions on Embedded Computing Systems (TECS). 2023.

• "Benchmarking Large Language Models for Automated Verilog RTL Code Generation". S. Thakur, B. Ahmad, Z. Fan, H. Pearce, B. Tan, R. Karri, B. Dolan-Gavitt, S. Garg. Design, Automation & Test in Europe Conference & Exhibition (DATE). 2023.

• "Lost at C: A user study on the security implications of large language model code assistants". G. Sandoval, H. Pearce, T. Nys, R. Karri, S. Garg, B. Dolan-Gavitt. USENIX. 2023.

• "Multi-Modal Side Channel Data Driven Golden-Free Detection of Software and Firmware Trojans", P. Krishnamurthy, V.R. Surabhi, H. Pearce, R. Karri, F. Khorrami. IEEE Transactions on Dependable and Secure Computing (TDSC). 2022

• "Application of micro-computed tomography for authentication of 3D printed composite parts",  G. Mac, M. Mandal, A. Rastogi, G. Gailani, H. Pearce, N. Gupta. Additive Manufacturing Letters. 2022.

• "Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design", B. Ahmad, W.-K. Liu, L. Collini, H. Pearce, J. M. Fung, J. Valamehr, M. Bidmeshki, P. Sapiecha, S. Brown, K. Chakrabarty, R. Karri, B. Tan. International Conference on Computer-Aided Design (ICCAD). 2022.

• "FLAW3D: A Trojan-based Cyber Attack on the Physical Outcomes of Additive Manufacturing", H. Pearce, K. Yanamandra, N. Gupta, R. Karri. IEEE Transactions on Mechatronics (TMECH). 2022.

• "Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks", H. Pearce, V. R. Surabhi, P. Krishnamurthy, J. Trujillo, R. Karri, F. Khorrami. IEEE Transactions on Very Large Scale Integration Systems (TVLSI). 2022.

• "Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributions", H. Pearce, B. Ahmad, B. Tan, B. Dolan-Gavitt, R. Karri. IEEE Symposium on Security and Privacy (SP / Oakland). 2022.

• "Formal Methods for the Security of Medical Devices", S. Pinisetty, N. Allen, H. Pearce, M. Trew, M. Singh Gaur, P. Roop. Applied Smart Health Care Informatics: A Computational Intelligence Perspective. 2022.

• "Determination of Fiber Content in 3D Printed Composite Parts Using Image Analysis", H. Srivastava, H. Pearce, G. Mac, N. Gupta. IEEE Embedded Systems Letters (ESL). 2022.

• "Needle in a Haystack: Detecting Subtle Malicious Edits to Additive Manufacturing G-code Files", C. Beckwith, H. S. Naicker, S. Mehta, V. R. Udapa, N.T. Tim, V. Gadre, H. Pearce, G. Mac, N. Gupta. IEEE Embedded Systems Letters (ESL). 2021.

• "Uncertainty quantification in dimensions dataset of additive manufactured NIST standard test artifact", G. Mac, H. Pearce, R. Karri, N. Gupta. Data in Brief. 2021.

• "DAVE: Deriving Automatically Verilog from English", H. Pearce, B. Tan, R. Karri. ACM/IEEE Workshop on Machine Learning for CAD (MLCAD) 2020.

• "Designing Neural Networks for Real-Time Systems", H. Pearce, X. Yang, P. S. Roop, M. Katzef, T. B. Strøm. IEEE Embedded Systems Letters (ESL). 2020.

• "A compositional approach using Keras for neural networks in real-time systems", X. Yang, P. Roop, H. Pearce, J. W. Ro. Design, Automation & Test in Europe Conference & Exhibition (DATE). 2020.

• "Securing implantable medical devices with runtime enforcement hardware", H. Pearce, M. M. Y. Kuo, P. S. Roop, S. Pinisetty. ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE). 2019.

• "Smart I/O modules for mitigating cyber-physical attacks on industrial control systems", H. Pearce, S. Pinisetty, P. S. Roop, M. M. Y. Kuo, A. Ukil. IEEE Transactions on Industrial Informatics (TII). 2019.

• "Synthesizing IEC 61499 Function Blocks to hardware", H. Pearce, P. Roop. IEIE/IEEE International Conference on Electronics, Information, and Communication (ICEIC). 2019.

• "Synchronus neural networks for cyber-physical systems", P. S. Roop, H. Pearce, K. Monadjem. ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE). 2018.

• "Faster function blocks for precision timed industrial automation", H. Pearce, P. Roop, M. Biglari-Abhari, M. Schoeberl. IEEE International Symposium on Real-Time Distributed Computing (ISORC). 2018.

• "Simulation of cyber-physical systems using IEC61499", H. A. Pearce, M. M. Y. Kuo, N. Allen, P. S. Roop, A. Malik. ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE). 2017.

• "A model driven approach for cardiac pacemaker design using a PRET processor", N. Allen, H. Pearce, P. Roop, R. von Hanxleden. IEEE International Symposium on Real-Time Distributed Computing (ISORC). 2017.

• "RunSync: A predictable runtime for precision timed automation systems", H. A. Pearce, M. M. Y. Kuo, P. S. Roop, M. Biglari-Abhari. 2016.

My thesis was titled "Model-driven Engineering for Safety and Security in Industry 4.0 ". It focused on how different engineering techniques can be utilized to test and verify different safety and security properties within different stages of the design lifecycle for industrial control and cyber-physical systems. This included work on precision-timed (PRET) architectures, modeling with IEC 61499, defining new semantics for control and plant lock-step simulation as well as for safety properties in a textual "Valued Discrete Timed Automata (VDTA)" format, and compilation tools for VDTA to Verilog.